Independent watchdog is started by writing the value 0xCCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. To refresh IDWG timer before it reaches zero, HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) function has to be used.

Reload – specifies the timer period, that is the auto-reload value when the timer is refreshed.

If prescaler is set to IWDG_PRESCALER_64 and reload value is set to 4096 then timeout period is about 8192ms approx. If prescaler is set to IWDG_PRESCALER_4 and reload value is set to 4096 then timeout period is about 512ms.Ģ. Init.Prescaler – prescaler value, and it can assume all powers of two ranging from 2² up to 2⁸.IWDG initialization IWDG_HandleTypeDef hiwdg In STM32 microcontrollers the independent watchdog (IWDG) is a 12-bit down-counter timer clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. Thus, a watchdog timer can be configured such that it will reach the end of its counting period only if a processor failure has occurred, and by forcing a system reset, the watchdog timer helps the processor to escape from the failure mode and continue normal operation. In order to prevent this, a processor must perform some type of specific action that resets the watchdog. If a watchdog timer reaches the end of its counting period, it resets the entire processor system. A watchdog timer is based on a counter that counts down from some initial value to zero. And this may have important costs, especially if the device is designed to work in dangerous and critical contexts.Ī watchdog timer is a specialized timer module that helps a microprocessor to recover from malfunctions. Apart from hardware faults, which can also impact on the software, even the most careful design may have some unexpected conditions that lead to abnormal behaviour of our device. Anything that can go wrong, will go wrong especially for embedded systems.

Watchdog government example